Merged memory logic (MML) is a complex semiconductor device which integrates a memory cell array and an analog or peripheral circuit in one chip. A great deal of research is underway to realize high-integration and high-speed semiconductor devices used for such a complex semiconductor device. For example, ardent research is being performed to realize a high-capacitance capacitor in analog circuits requiring high-speed operation.
In polysilicon-insulator-polysilicon (PIP) capacitors, an upper electrode and a lower electrode are made of conductive polysilicon, thus causing oxidation reactions on the interfaces between dielectric thin film and the upper and lower electrodes. The oxidation reaction causes formation of native oxide films, thus disadvantageously reducing overall capacitance. Another disadvantage is that PIP capacitors have a low capacitance due to depletion regions formed on the polysilicon layer and are thus unsuitable for high-speed and high-frequency operations.
In order to mitigate the disadvantages of PIP capacitors, metal-insulator-metal (MIM) capacitors may be used. A MIM capacitor has a structure in which a lower metal, an insulating layer and an upper metal are laminated, in that order. The MIM capacitor has a low specific resistance and is free from parasitic capacitance by depletion, thus being generally applicable in high-performance semiconductor devices.
In order to realize such a MIM capacitor in semiconductor devices, in addition to photoresist patterns to form metal line patterns, separate photoresist patterns to form the MIM capacitor are required.